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general description the max17632 family of parts (max17632a, max17632b and max17632c) is a high-efficiency, high-voltage, syn - chronous step-down dc-dc converter with integrated mosfets operating over an input-voltage range of 4.5v to 36v. it can deliv er up to 2a current. the max17632a and max17632b are fixed 3.3v and fixed 5v output parts, respectively. the max17632c is an adjustable output voltage (0.9v to 90% of v in ) part. built-in compensation across the output-voltage range eliminates the need for external compensation components. the max17632 features peak-current-mode control archi - tecture. the device can be operated in the forced pulse- width modulation (pwm), or pulse-frequency modulation (pfm), or discontinuous-conduction mode (dcm) to enable high efficiency under full-load and light-load conditions. the max17632 offers a low minimum on time that allows high switching frequencies and a smaller solution size. the feedback-voltage regulation accuracy over -40c to +125c for the max17632a/max17632b/max17632c is 1.2%.the device is available in a 16-pin (3mm x 3mm) tqfn package. simulation models are available. applications industrial control power supplies general-purpose point-of-load distributed supply regulation base station power supplies wall transformer regulation high voltage single-board systems ordering information appears at end of data sheet. 19-100164; rev 0; 9/17 benefts and features reduces external components and total cost ? no schottky - synchronous operation ? internal compensation components ? all-ceramic capacitors, compact layout reduces number of dc-dc regulators to stock ? wide 4.5v to 36v input ? adjustable output range from 0.9v to 90% of v in ? delivers up to 2a over temperature range ? 400khz to 2.2mhz adjustable frequency with external clock synchronization ? available in a 16-pin, 3mm x 3mm tqfn package reduces power dissipation ? peak effciency > 90% ? pfm and dcm modes enable enhanced light- load effciency ? auxiliary bootstrap supply (extvcc) for improved effciency ? 2.8a shutdown current operates reliably in adverse industrial environments ? hiccup-mode overload protection ? adjustable and monotonic startup with prebiased output voltage ? built-in output-voltage monitoring with reset ? programmable en/uvlo threshold ? overtemperature protection ? high industrial -40c to +125c ambient operating temperature range / -40c to +150c junction temperature range max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter evaluation kit available
typical application circuit reset en/uvlo v in bst rt mode/sync v cc sgnd ss fb pgnd lx lx v in c5 5600pf extvcc 2.2f 0.1f 10h 22f v out 5v, 2a max17632b v in c2 c1 c4 l1 pgnd 6.5v - 36v 2.2f c3 c1: grm31cr71h225ka88 l1: xal5050-103me c4: grm32er71a226k f sw : 400khz mode: pwm ep maxim integrated g 2 www.maximintegrated.com max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter
package type: 16-pin tqfn package code t1633+5c outline number 21-0136 land pattern number 90-0032 thermal resistance, four-layer board (n ote 2) junction to ambient ( ja ) 38 oc/w junction to case ( jc ) 10 oc/w v in to pgnd ......................................................... -0.3v to +40v en/uvlo to sgnd ...................................... -0.3v to v in + 0.3v lx to pgnd .................................................. -0.3v to v in + 0.3v extvcc to sgnd ............................................... -5.5v to +6.5v bst to pgnd ..................................................... -0.3v to +46.5v bst to lx ............................................................. -0.3v to +6.5v bst to v cc ........................................................... -0.3v to +40v reset , ss, mode/sync, v cc , rt to sgnd ... -0.3v to +6.5v fb to sgnd (max17632a & max17632b) ........... -5.5v to 6.5v fb to sgnd (max17632c) .................................. -0.3v to 6.5v pgnd to sgnd .................................................... -0.3v to +0.3v lx total rms current .......................................................... 3.5a output short-circuit duration .................................... continuous continuous power dissipation (multilayer board) (t a = +70c, derate 20.8mw/c above +70c.) .... 1666.7mw operating temperature range (note 1) .............. -40c to 125c junction temperature ...................................................... +150c storage temperature range ............................ -65c to +150c lead temperature (soldering, 10s) ................................. +300c soldering temperature (reflow) ....................................... +260c (v in = v en/uvlo = 24v, r rt = unconnected (f sw = 400 khz), c vcc = 2.2f, v mode/sync = v extvcc = v sgnd = v pgnd = 0v, v fb = 3.67v (max17632a), v fb = 5.5v (max17632b), v fb = 1v (max17632c), lx = ss = reset = open, v bst to v lx = 5v, t a = -40c to 125c, unless otherwise noted. typical values are at t a = +25c. all voltages are referenced to sgnd, unless otherwise noted.) (note 3 ) parameter symbol conditions min typ max units input supply (v in ) input-voltage range v in 4.5 36 v input-shutdown current i in-sh v en/uvlo = 0v (shutdown mode) 2.8 4.5 a input-quiescent current i q_pfm mode/sync = open, v extvcc = 5v 50 a mode/sync = open, r rt = 50.8k?, v extvcc = 5v 60 i q_dcm dcm mode, v lx = 0.1v 1.2 1.8 ma i q_pwm normal switching mode, f sw = 400khz, v fb = 3v (max17632a), v fb = 4.4v (max17632b), v fb = 0.8v (max17632c) 5 absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to ab solute maximum rating conditions for extended periods may affect device reliability. note 1: junction temperature greater than +125c degrades operating lifetimes. note 2: package thermal resistances were obtained using the max17632 evaluation kit. for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package information electrical characteristics maxim integrated 3 www.maximintegrated.com max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter
(v in = v en/uvlo = 24v, r rt = unconnected (f sw = 400 khz), c vcc = 2.2f, v mode/sync = v extvcc = v sgnd = v pgnd = 0v, v fb = 3.67v (max17632a), v fb = 5.5v (max17632b), v fb = 1v (max17632c), lx = ss = reset = open, v bst to v lx = 5v, t a = -40c to 125c, unless otherwise noted. typical values are at t a = +25c. all voltages are referenced to sgnd, unless otherwise noted.) (note 3 ) parameter symbol conditions min typ max units enable/uvlo (en/uvlo) en/uvlo threshold v enr v en/uvlo rising 1.19 1.215 1.26 v v enf v en/uvlo falling 1.068 1.09 1.131 en input-leakage current i en v en/uvlo = 0v, t a = +25oc -50 0 +50 na v cc (ldo) v cc output-voltage range v cc 1ma i vcc 15ma 4.75 5 5.25 v 6v v in 36v, i vcc = 1ma 4.75 5 5.25 v cc current limit i vcc-max v cc = 4.5v, v in = 7.5v 25 50 ma v cc dropout v cc-do v in = 4.5v, i vcc = 10ma 0.3 v v cc uvlo v cc_uvr v cc rising 4.05 4.2 4.3 v v cc_uvf v cc falling 3.65 3.8 3.9 extvcc extvcc switchover threshold v extvcc rising 4.56 4.7 4.84 v v extvcc falling 4.3 4.45 4.6 power mosfets high-side nmos on- resistance r ds-onh i lx = 0.3a, sourcing 125 250 m low-side nmos on-resistance r ds-onl i lx = 0.3a, sinking 80 160 m lx leakage current i lx_lkg v lx = (v pgnd +1v) to (v in - 1v), t a = +25c -2 +3 a soft-start (ss) charging current i ss v ss = 0.5v 4.7 5 5.3 a feedback (fb) fb regulation voltage v fb-reg mode/sync = sgnd or mode/sync = v cc , for max17632a 3.26 3.3 3.34 v mode/sync = sgnd or mode/sync = v cc , for max17632b 4.94 5 5.06 mode/sync = sgnd or mode/sync = v cc , for max17632c 0.889 0.9 0.911 mode/sync = open, for max17632a 3.26 3.36 3.43 mode/sync = open, for max17632b 4.94 5.09 5.20 mode/sync = open, for max17632c 0.89 0.915 0.936 fb input-bias current i fb for max17632a 21 a for max17632b 17 0 v fb 1v, t a = 25oc, for max17632c -50 +50 na electrical characteristics (continued) maxim integrated 4 www.maximintegrated.com max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter
(v in = v en/uvlo = 24v, r rt = unconnected (f sw = 400 khz), c vcc = 2.2f, v mode/sync = v extvcc = v sgnd = v pgnd = 0v, v fb = 3.67v (max17632a), v fb = 5.5v (max17632b), v fb = 1v (max17632c), lx = ss = reset = open, v bst to v lx = 5v, t a = -40c to 125c, unless otherwise noted. typical values are at t a = +25c. all voltages are referenced to sgnd, unless otherwise noted.) (note 3 ) parameter symbol conditions min typ max units mode/sync mode threshold v m-dcm mode/sync = v cc (dcm mode) v cc - 0.65 v v m-pfm mode/sync = open (pfm mode) v cc /2 v m-pwm mode/sync = sgnd (pwm mode) 0.75 sync frequency-capture range f sync f sw set by r rt 1.1 x f sw 1.4 x f sw khz sync pulse width 50 ns sync threshold v ih 2.1 v v il 0.8 current limit peak current-limit threshold i peak- limit 2.7 3.15 3.6 a runaway peak current- limit threshold i runaway- limit 3 3.6 4.1 a pfm peak current-limit threshold i pfm mode/sync = open 0.8 a valley current-limit threshold i valley- limit mode/sync = open or mode/sync = v cc -0.15 0 +0.15 a mode/sync = sgnd, v fb > 0.65 -1.8 rt switching frequency f sw r rt = 50.8k 380 400 420 khz r rt = 40.2k 475 500 525 r rt = 8.06k 1950 2200 2450 r rt = open 370 400 430 v fb undervoltage trip level to cause hiccup v fb-hicf for max17632a 2.05 2.13 2.2 v for max17632b 3.11 3.22 3.33 for max17632c 0.56 0.58 0.6 hiccup timeout (note 4) 32768 cycles minimum on-time t on-min 52 80 ns minimum off-time t off-min 140 160 ns lx dead time lx dt 5 ns electrical characteristics (continued) maxim integrated 5 www.maximintegrated.com max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter
note 3: electrical specifications are production tested at t a = +25 c. specifications over the entire operating temperature range are guaranteed by design and characterization. note 4: see the overcurrent protection (ocp)/hiccup mode section for more details (v in = v en/uvlo = 24v, r rt = unconnected (f sw = 400 khz), c vcc = 2.2f, v mode/sync = v extvcc = v sgnd = v pgnd = 0v, v fb = 3.67v (max17632a), v fb = 5.5v (max17632b), v fb = 1v (max17632c), lx = ss = reset = open, v bst to v lx = 5v, t a = -40c to 125c, unless otherwise noted. typical values are at t a = +25c. all voltages are referenced to sgnd, unless otherwise noted.) (note 3 ) parameter symbol conditions min typ max units reset reset output-level low v resetl i reset = 10ma 400 mv reset output-leakage current i resetlkg t a = t j = 25oc, v reset = 5.5v -100 100 na fb threshold for reset deassertion v fb-okr v fb rising 93.8 95 97.8 % fb threshold for reset assertion v fb-okf v fb falling 90.5 92 94.6 % reset delay after fb reaches 95% regulation 1024 cycles thermal shutdown (temp) thermal-shutdown threshold temperature rising 165 c thermal-shutdown hysteresis 10 c electrical characteristics (continued) maxim integrated 6 www.maximintegrated.com max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter
(v en/uvlo = v in = 24v, v sgnd = v pgnd = 0v, c vcc = 2.2f, c bst = 0.1f, c ss = 5600pf, t a = -40c to +125c, unless otherwise noted. typical values are at t a = +25c. all voltages are referenced to sgnd, unless otherwise noted.) typical operating characteristics 0 10 20 30 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 efficiency (%) load current (a) max17632a efficiency vs . load current figure 3 circuit v in = 36v v in = 24v v in = 12v v in = 4.5v toc01 conditions: fixed 3.3v output, pwm mode, f sw = 400 k h z 0 10 20 30 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 efficiency (%) load current (a) max17632b efficiency vs . load current figure 4 circuit v in = 36v v in = 24v v in = 12v v in = 6.5v toc04 conditions: fixed 5v output, pwm mode, f sw = 400 k h z 0 10 20 30 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 efficiency (%) load current (a) max17632c efficiency vs . load current figure 7 circuit v in = 28v v in = 24v v in = 12v v in = 5.5v toc07 conditions: adjustable 3.3v output, pwm mode, f sw = 1mh z 20 30 40 50 60 70 80 90 100 0.01 0.1 1 efficiency (%) load current (a) max17632a efficiency vs . load current figure 3 circuit v in = 36v v in = 24v v in = 12v v in = 4.5v toc02 conditions: fixed 3.3v output, dcm mode, f sw = 400 k h z 30 40 50 60 70 80 90 100 0.01 0.1 1 efficiency (%) load current (a) max17632b efficiency vs . load current figure 4 circuit v in = 36v v in = 24v v in = 12v v in = 6.5v toc05 conditions: fixed 5v output, dcm mode, f sw = 400 k h z 20 30 40 50 60 70 80 90 100 0.01 0.1 1 efficiency (%) load current (a) max17632c efficiency vs . load current figure 7 circuit v in = 28v v in = 24v v in = 12v v in = 5.5v toc08 conditions: adjustable 3.3v output, dcm mode, f sw = 1mh z 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 efficiency (%) load current (a) max17632a efficiency vs . load current figure 3 circuit v in = 36v v in = 24v v in = 12v v in = 4.5v toc03 conditions: fixed 3.3v output, pfm mode, f sw = 400 k h z 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 efficiency (%) load current (a) max17632b efficiency vs . load current figure 4 circuit v in = 36v v in = 24v v in = 12v v in = 6.5v toc06 conditions: fixed 5v output, pfm mode, f sw = 400 k h z 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 efficiency (%) load current (a) max17632c efficiency vs . load current figure 7 circuit v in = 28v v in = 24v v in = 12v v in = 5.5v toc09 conditions: adjustable 3.3v output, pfm mode, f sw = 1mh z maxim integrated 7 www.maximintegrated.com max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter
(v en/uvlo = v in = 24v, v sgnd = v pgnd = 0v, c vcc = 2.2f, c bst = 0.1f, c ss = 5600pf, t a = -40c to +125c, unless otherwise noted. typical values are at t a = +25c. all voltages are referenced to sgnd, unless otherwise noted.) typical operating characteristics (continued) 3.28 3.29 3.30 3.31 3.32 0.0 0.5 1.0 1.5 2.0 output voltage (v) load current (a) max17632a load and line regulation figure 3 circuit v in = 12v v in = 4.5v v in = 36v toc10 v in = 24v conditions: fixed 3.3v output, pwm mode, f sw = 400 k h z 4.98 4.99 5.00 5.01 5.02 0.0 0.5 1.0 1.5 2.0 output voltage (v) load current (a) max17632b load and line regulation figure 4 circuit v in = 24v v in = 12v v in = 6.5v v in = 36v toc13 conditions: fixed 5v output, pwm mode, f sw = 400 k h z 3.28 3.29 3.30 3.31 3.32 0.00 0.50 1.00 1.50 2.00 output voltage (v) load current (a) max17632c load and line regulation figure 7 circuit v in = 24v v in = 12v v in = 5.5v v in = 28v toc16 conditions: adjustable 3.3v output, pwm mode, f sw = 1mh z 3.28 3.29 3.30 3.31 3.32 0.0 0.5 1.0 1.5 2.0 output voltage (v) load current (a) max17632a load and line regulation figure 3 circuit v in = 24v v in = 12v v in = 4.5v v in = 36v toc11 conditions: fixed 3.3v output, dcm mode, f sw = 400 k h z 4.98 4.99 5.00 5.01 5.02 0.0 0.5 1.0 1.5 2.0 output voltage (v) load current (a) max17632b load and line regulation figure 4 circuit v in = 24v v in = 6.5v v in = 36v toc14 v in = 12v conditions: fixed 5v output, dcm mode, f sw = 400 k h z 3.28 3.29 3.30 3.31 3.32 0.0 0.5 1.0 1.5 2.0 output voltage (v) load current (a) max17632c load and line regulation figure 7 circuit v in = 24v v in = 12v v in = 5.5v v in = 28v toc17 conditions: adjustable 3.3v output, dcm mode, f sw = 1mh z 3.20 3.24 3.28 3.32 3.36 3.40 0.0 0.5 1.0 1.5 2.0 output voltage (v) load current (a) max17632a load and line regulation figure 3 circuit v in = 24v v in = 12v v in = 4.5v v in = 36v toc12 conditions: fixed 3.3v output, pfm mode, f sw = 400 k h z 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 0.0 0.5 1.0 1.5 2.0 output voltage (v) load current (a) max17632b load and line regulation figure 4 circuit v in = 24v v in = 12v v in = 6.5v v in = 36v toc15 conditions: fixed 5v output, pfm mode, f sw = 400 k h z 3.28 3.30 3.32 3.34 3.36 3.38 3.40 0.0 0.5 1.0 1.5 2.0 output voltage (v) load current (a) max17632c load and line regulation figure 7 circuit v in = 24v v in = 12v v in = 5.5v v in = 28v toc18 conditions: adjustable 3.3v output, pfm mode, f sw = 1mh z maxim integrated 8 www.maximintegrated.com max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter
(v en/uvlo = v in = 24v, v sgnd = v pgnd = 0v, c vcc = 2.2f, c bst = 0.1f, c ss = 5600pf, t a = -40c to +125c, unless otherwise noted. typical values are at t a = +25c. all voltages are referenced to sgnd, unless otherwise noted.) typical operating characteristics (continued) 5v/div 5v/div 1ms/div v en/uvlo max17632a soft - start/shutdown from en/uvlo figure 3 circuit toc19 2v/div v out i lx v reset 2a/div conditions: fixed 3.3v output, pwm mode, 2a load, f sw = 400 k h z 5v/div 5v/div 1ms/div v en/uvlo max17632a soft - start with pre - bias voltage of 1.65v figure 3 circuit toc22 1v/div v out i lx v reset 1a/div conditions: fixed 3.3v output, pwm mode, 20 m a load, f sw = 400 k h z 20v/div 2s/div v out(ac) max17632a steady state figure 3 circuit toc25 20mv/div v lx i lx 2a/div conditions: fixed 3.3v output, pwm mode, 2a load, f sw = 400 k h z 5v/div 5v/div 1ms/div v en/uvlo max17632b soft - start/shutdown from en/uvlo figure 4 circuit toc20 2v/div v out i lx v reset 2a/div conditions: fixed 5v output, pwm mode, 2a load, f sw = 400 k h z 5v/div 5v/div 1ms/div v en/uvlo max17632b soft - start with pre - bias voltage of 2.5v figure 4 circuit toc23 2v/div v out i lx v reset 1a/div conditions: fixed 5v output, pwm mode, 20 m a load, f sw = 400 k h z 20v/div 1s/div v out(ac) max17632a steady state figure 3 circuit toc26 20mv/div v lx i lx 0.5a/div conditions: fixed 3.3v output, dcm mode, 20 m a load, f sw = 400 k h z 5v/div 5v/div 1ms/div v en/uvlo max17632c soft - start/shutdown from en/uvlo figure 7 circuit toc21 1v/div v out i lx v reset 2a/div conditions: adjustable 3.3v output, pwm mode, 2a load, f sw = 1mh z 5v/div 5v/div 1ms/div v en/uvlo max17632c soft - start with pre - bias voltage of 1.65v figure 7 circuit toc24 1v/div v out i lx v reset 1a/div conditions: adjustable 3.3v output, pwm mode, 20 m a load, f sw = 1mh z 20v/div 40s/div v out(ac) max17632a steady state figure 3 circuit toc27 50mv/div v lx i lx 0.5a/div conditions: fixed 3.3v output, pfm mode, 20 m a load, f sw = 400 k h z maxim integrated 9 www.maximintegrated.com max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter
(v en/uvlo = v in = 24v, v sgnd = v pgnd = 0v, c vcc = 2.2f, c bst = 0.1f, c ss = 5600pf, t a = -40c to +125c, unless otherwise noted. typical values are at t a = +25c. all voltages are referenced to sgnd, unless otherwise noted.) typical operating characteristics (continued) 20v/div 2s/div v out(ac) max17632b steady state figure 4 circuit toc28 20mv/div v lx i lx 2a/div conditions: fixed 5v output, pwm mode, 2a load, f sw = 400 k h z 20v/div 2s/div v out(ac) max17632c steady state figure 5 circuit toc31 20mv/div v lx i lx 2a/div conditions: adjustable 3.3v output, pwm mode, 2a load, f sw = 400 k h z 20v/div 2s/div v out(ac) max17632c steady state figure 6 circuit toc34 20mv/div v lx i lx 2a/div conditions: adjustable 5v output, pwm mode, 2a load, f sw = 400 k h z 20v/div 1s/div v out(ac) max17632b steady state figure 4 circuit toc29 20mv/div v lx i lx 0.5a/div conditions: fixed 5v output, dcm mode, 20 m a load, f sw = 400 k h z 20v/div 1s/div v out(ac) max17632c steady state figure 5 circuit toc32 20mv/div v lx i lx 0.5a/div conditions: adjustable 3.3v output, dcm mode, 20 m a load, f sw = 400 k h z 20v/div 1s/div v out(ac) max17632c steady state figure 6 circuit toc35 20mv/div v lx i lx 0.5a/div conditions: adjustable 5v output, dcm mode, 20 m a load, f sw = 400 k h z 20v/div 40s/div v out(ac) max17632b steady state figure 4 circuit toc30 100mv/div v lx i lx 0.5a/div conditions: fixed 5v output, pfm mode, 20 m a load, f sw = 400 k h z 20v/div 40s/div v out(ac) max17632c steady state figure 5 circuit toc33 50mv/div v lx i lx 0.5a/div conditions: adjustable 3.3v output, pfm mode, 20 m a load, f sw = 400 k h z 20v/div 40s/div v out(ac) max17632c steady state figure 6 circuit toc36 100mv/div v lx i lx 0.5a/div conditions: adjustable 5v output, pfm mode, 20 m a load, f sw = 400 k h z maxim integrated 10 www.maximintegrated.com max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter
(v en/uvlo = v in = 24v, v sgnd = v pgnd = 0v, c vcc = 2.2f, c bst = 0.1f, c ss = 5600pf, t a = -40c to +125c, unless otherwise noted. typical values are at t a = +25c. all voltages are referenced to sgnd, unless otherwise noted.) typical operating characteristics (continued) 20v/div 1s/div v out(ac) max17632c steady state figure 7 circuit toc37 20mv/div v lx i lx 2a/div conditions: adjustable 3.3v output, pwm mode, 2a load, f sw = 1mh z 50mv/div 100s/div max17632a load transient between 0a and 1a figure 3 circuit toc40 v out(ac) i out 0.5a/div conditions: fixed 3.3v output, pwm mode, f sw = 400 k h z 100mv/div 400s/div max17632a load transient between 20 m a and 1a figure 3 circuit toc43 v out(ac) i out 0.5a/div conditions: fixed 3.3v output, pfm mode, f sw = 400 k h z 20v/div 1s/div v out(ac) max17632c steady state figure 7 circuit toc38 20mv/div v lx i lx 0.5a/div conditions: adjustable 3.3v output, dcm mode, 20 m a load, f sw = 1mh z 50mv/div 100s/div max17632a load transient between 1a and 2a figure 3 circuit toc41 v out(ac) i out 1a/div conditions: fixed 3.3v output, pwm mode, f sw = 400 k h z 100mv/div 100s/div max17632b load transient between 0a and 1a figure 4 circuit toc44 v out(ac) i out 0.5a/div conditions: fixed 5v output, pwm mode, f sw = 400 k h z 20v/div 20s/div v out(ac) max17632c steady state figure 7 circuit toc39 50mv/div v lx i lx 0.5a/div conditions: adjustable 3.3v output, pfm mode, 20 m a load, f sw = 1mh z 100mv/div 200s/div max17632a load transient between 20 m a and 1a figure 3 circuit toc42 v out(ac) i out 0.5a/div conditions: fixed 3.3v output, dcm mode, f sw = 400 k h z 100mv/div 100s/div max17632b load transient between 1a and 2a figure 4 circuit toc45 v out(ac) i out 1a/div conditions: fixed 5v output, pwm mode, f sw = 400 k h z maxim integrated 11 www.maximintegrated.com max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter
(v en/uvlo = v in = 24v, v sgnd = v pgnd = 0v, c vcc = 2.2f, c bst = 0.1f, c ss = 5600pf, t a = -40c to +125c, unless otherwise noted. typical values are at t a = +25c. all voltages are referenced to sgnd, unless otherwise noted.) typical operating characteristics (continued) 200mv/div 200s/div max17632b load transient between 20 m a and 1a figure 4 circuit toc46 v out(ac) i out 0.5a/div conditions: fixed 5v output, dcm mode, f sw = 400 k h z 100mv/div 100s/div max17632c load transient between 1a and 2a figure 6 circuit toc49 v out(ac) i out 1a/div conditions: adjustable 5v output, pwm mode, f sw = 400 k h z 100mv/div 200s/div max17632c load transient between 20 m a and 1a figure 7 circuit toc52 v out(ac) i out 0.5a/div conditions: adjustable 3.3v output, dcm mode, f sw = 1mh z 200mv/div 400s/div max17632b load transient between 20 m a and 1a figure 4 circuit toc47 v out(ac) i out 0.5a/div conditions: fixed 5v output, pfm mode, f sw = 400 k h z 50mv/div 100s/div max17632c load transient between 0a and 1a figure 7 circuit toc50 v out(ac) i out 0.5a/div conditions: adjustable 3.3v output, pwm mode, f sw = 1mh z 100mv/div 400s/div max17632c load transient between 20 m a and 1a figure 7 circuit toc53 v out(ac) i out 0.5a/div conditions: adjustable 3.3v output, pfm mode, f sw = 1mh z 50mv/div 100s/div max17632c load transient between 1a and 2a figure 5 circuit toc48 v out(ac) i out 1a/div conditions: adjustable 3.3v output, pwm mode, f sw = 400 k h z 50mv/div 100s/div max17632c load transient between 1a and 2a figure 7 circuit toc51 v out(ac) i out 1a/div conditions: adjustable 3.3v output, pwm mode, f sw = 1mh z 0.5v/div 2a/div 20ms/div v out max17632a overload protection figure 3 circuit toc54 i lx conditions: fixed 3.3v output, pwm mode, 4a load, f sw = 400 k h z maxim integrated 12 www.maximintegrated.com max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter
(v en/uvlo = v in = 24v, v sgnd = v pgnd = 0v, c vcc = 2.2f, c bst = 0.1f, c ss = 5600pf, t a = -40c to +125c, unless otherwise noted. typical values are at t a = +25c. all voltages are referenced to sgnd, unless otherwise noted.) typical operating characteristics (continued) 0.5v/div 2a/div 20ms/div v out max17632b overload protection figure 4 circuit toc55 i lx conditions: fixed 5v output, pwm mode, 4a load, f sw = 400 k h z 5v/div 50mv/div 2s/div v lx max17632a external clock synchronization figure 3 circuit toc58 v sync v out(ac) 10v/div i lx 2a/div conditions: fixed 3.3v output, pwm mode, 2a load, f sw = 560 k h z 5v/div 20mv/div 1s/div v lx max17632c external clock synchronization figure 7 circuit toc61 v sync v out(ac) 10v/div i lx 2a/div conditions: adjustable 3.3v output, pwm mode, 2a load, f sw = 1.1mh z 0.5v/div 2a/div 10ms/div v out max17632c overload protection figure 7 circuit toc56 i lx conditions: adjustable 3.3v output, pwm mode, 4a load, f sw = 1mh z 5v/div 50mv/div 2s/div v lx max17632b external clock synchronization figure 4 circuit toc59 v sync v out(ac) 10v/div i lx 2a/div conditions: fixed 5v output, pwm mode, 2a load, f sw = 440 k h z 5v/div 50mv/div 2s/div v lx max17632a external clock synchronization figure 3 circuit toc57 v sync v out(ac) 10v/div i lx 2a/div conditions: fixed 3.3v output, pwm mode, 2a load, f sw = 440 k h z 5v/div 50mv/div 2s/div v lx max17632b external clock synchronization figure 4 circuit toc60 v sync v out(ac) 10v/div i lx 2a/div conditions: fixed 5v output, pwm mode, 2a load, f sw = 560 k h z 5v/div 20mv/div 1s/div v lx max17632c external clock synchronization figure 7 circuit toc62 v sync v out(ac) 10v/div i lx 2a/div conditions: adjustable 3.3v output, pwm mode, 2a load, f sw = 1.4mh z maxim integrated 13 www.maximintegrated.com max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter
(v en/uvlo = v in = 24v, v sgnd = v pgnd = 0v, c vcc = 2.2f, c bst = 0.1f, c ss = 5600pf, t a = -40c to +125c, unless otherwise noted. typical values are at t a = +25c. all voltages are referenced to sgnd, unless otherwise noted.) typical operating characteristics (continued) -120 -90 -60 -30 0 30 60 90 120 1k 10k 100k -80 -60 -40 -20 0 20 40 60 80 phase ( ) gain (db) frequency (hz) gain toc64 phase gain crossover frequency = 46 khz phase margin = 64.8 max17632b closed - loop bode plot figure 4 circuit conditions: fixed 5v output, pwm mode, 2a load, f sw = 400 k h z -120 -90 -60 -30 0 30 60 90 120 1k 10k 100k -80 -60 -40 -20 0 20 40 60 80 phase ( toc66 gain crossover frequency = 43 khz phase margin = 69.5 max17632c closed - loop bode plot figure 6 circuit conditions adustable 5v output pwm mode 2a load sw 400 h phase -120 -90 -60 -30 0 30 60 90 120 1k 10k 100k -60 -40 -20 0 20 40 60 phase ( ) gain (db) frequency (hz) gain toc65 phase gain crossover frequency = 41 khz phase margin = 64.2 max17632c closed - loop bode plot figure 5 circuit conditions adustable 3.3v output pwm mode 2a load sw 400 h -120 -0 -60 -30 0 30 60 0 120 1 10 100 -60 -40 -20 0 20 40 60 phase toc67 phase gain crossover frequency = 83.5 khz phase margin = 61 max17632c closed - loop bode plot figure 7 circuit conditions adustable 3.3v output pwm mode 2a load sw 1mh -0 -60 -30 0 30 60 0 1 10 100 -60 -40 -20 0 20 40 60 phase toc63 phase crossover frequency = 39.9 khz phase margin = 63.9 max17632a closed - loop bode plot figure 3 circuit conditions fixed 3.3v output pwm mode 2a load sw 400 h maxim integrated 14 www.maximintegrated.com max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter
pin name function 1 en/uvlo enable/undervoltage lockout pin. drive en/uvlo high to enable the output. connect to the center of the resistor-divider between v in and sgnd to set the input voltage at which the part turns on. connect to v in pins for always on operation. pull low for disabling the device. 2 v cc 5v ldo output. bypass v cc with a 2.2f ceramic capacitance to sgnd. 3 sgnd analog ground 4 mode/ sync mode/sync pin confgures the device to operate either in pwm, pfm or dcm modes of operation. leave mode/sync unconnected for pfm operation (pulse skipping at light loads). connect mode/sync to sgnd for constant-frequency pwm operation at all loads. connect mode/sync to v cc for dcm operation at light loads.the device can be synchronized to an external clock using this pin. see the mode selection and external synchronization (mode/sync) section for more details. 5 ss soft-start input. connect a capacitor from ss to sgnd to set the soft-start time. 6 fb feedback input. connect the output voltage node (v out ) to fb for max17632a and max17632b. connect fb to the center node of an external resistor-divider from the output to sgnd to set the output voltage for max17632c. see the adjusting output voltage section for more details. 7 rt connect a resistor from rt to sgnd to set the regulators switching frequency between 400khz and 2.2mhz. leave rt open for the default 400khz frequency. see the setting the switching frequency (rt) section for more details. 8 reset open-drain reset output. the reset output is driven low if fb drops below 92% of its set value. reset goes high 1024 cycles after fb rises above 95% of its set value. 9 extvcc external power supply input reduces the internal-ldo loss. connect it to buck output when it is programmed to 5v only. when extvcc is not used, connect it to sgnd. 10 bst boost flying capacitor. connect a 0.1f ceramic capacitor between bst and lx. 11, 12 lx switching node pins. connect lx pins to the switching side of the inductor. 13, 14 pgnd power ground pins of the converter. connect externally to the power ground plane. refer to the max17632 evaluation kit data sheet for a layout example. 15, 16 v in power-supply input pins. 4.5v to 36v input-supply range. decouple to pgnd with a 2.2f capacitor; place the capacitor close to the v in and pgnd pins. - ep exposed pad. always connect ep to the sgnd pin of the ic. also, connect ep to a large sgnd plane with several thermal vias for best thermal performance. refer to the max17632 evkit data sheet for an example of the correct method for ep connection and thermal vias. pin confguration 16 -pin tqfn 3mm 3mm top view max17632a max17632b max17632c ep v in sgnd v cc v in bst en/uvlo pgnd pgnd lx extvcc 5 mode/sync lx 16 15 14 13 1 2 3 4 6 7 8 12 11 10 9 ss fb rt reset pin description maxim integrated 15 www.maximintegrated.com max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter
functional diagrams block diagram sgnd ldo v cc lx v in pgnd bst mode/sync ss v cc hiccup fb pwm/pfm/ hiccup logic rt reset en/uvlo fb switchover logic error amplifier/ loop compensation reset logic mode selection logic oscillator slope compensation current-sense logic max17632a/max17632b/ max17632c hiccup 5v 1.215v 5a extvcc thermal shutdown sync sync r1 r2 *s2 *s1 *s1 - close, *s2 - open for max17632c *s1 - open, *s2 - close for max17632a/max17632b r1 - 246.24k?, r2 - 54k? for max17632b r1 - 115.2k?, r2 - 43.2k? for max17632a enok enok maxim integrated 16 www.maximintegrated.com max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter
detailed description the max17632 family of devices (max17632a, max17632b and max17632c) is a high-efficiency, high- voltage, synchronous step-down dc-dc converter with integrated mosfets operating over an input-voltage range of 4.5v to 36v. it can deliver up to 2a current. max17632a and max17632b are fixed 3.3v and fixed 5v output parts, respectively. max17632c is the adjustable output voltage (0.9v to 90% of v in ) part. built-in com - pensation across the output-voltage range eliminates the need for external compensation components. the feed - back-voltage regulation accuracy over -40c to +125c is 1.2% for max17632a/max17632b/max17632c. the device features a peak-current-mode control archi - tecture. an internal transconductance error amplifier produces an integrated error voltage at an internal node, which sets the duty cycle using a pwm comparator, a high-side current-sense amplifier, and a slope-compen - sation generator. at each rising edge of the clock, the high-side mosfet turns on and remains on until either the appropriate or maximum duty cycle is reached, or the peak current limit is detected. during the high-side mosfets on-time, the inductor current ramps up. during the second half of the switching cycle, the high-side mosfet turns off and the low-side mosfet turns on. the inductor releases the stored energy as its current ramps down and provides current to the output. the device features a mode/sync pin that can be used to operate the device in pwm, or pfm, or dcm control modes. the device integrates adjustable-input undervolt - age lockout, adjustable soft-start, open-drain reset , and external frequency synchronization features. the max17632 offers a low minimum on time that allows high switching frequencies and a smaller solution size. mode selection and external synchronization (mode/sync) the logic state of the mode/sync pin is latched when v cc and en/uvlo voltages exceed the respective uvlo rising thresholds and all internal voltages are ready to allow lx switching. if the state of the mode/sync pin is open at power-up, the device operates in pfm mode at light loads. if the state of the mode/sync pin is low (connected to sgnd) at power-up, the device operates in constant-frequency pwm mode at all loads. if the state of the mode/sync pin is high (connected to v cc ) at power-up, the device operates in constant-frequency dcm mode at light loads. state changes on the mode/ sync pin are ignored during normal operation. the internal oscillator of the device can be synchronized to an external clock signal through the mode/sync pin. the external synchronization clock frequency must be between 1.1 x f sw and 1.4 x f sw , where f sw is the switching frequency programmed by the resistor con - nected at the rt pin. when an external clock is applied to the mode/sync pin, the internal oscillator frequency changes to the external clock frequency (from the original frequency based on rt setting). the minimum external clock pulse-width should be greater than 50ns. see the mode/sync section in the electrical characteristics table for details. pwm mode operation in pwm mode, the inductor current is allowed to go nega - tive. pwm operation provides constant frequency opera - tion at all loads, and is useful in applications sensitive to switching frequency. however, the pwm mode of opera - tion gives lower efficiency at light loads compared to pfm and dcm modes of operation. pfm mode operation pfm mode of operation disables negative inductor cur - rent and additionally skips pulses at light loads for high efficiency. in pfm mode, the inductor current is forced to a fixed peak of i pfm (800ma (typ)) every clock cycle until the output rises to 102.3% of the set nominal output volt - age. once the output reaches 102.3% of the set nominal output voltage, both the high-side and low-side fets are turned off and the device enters hibernate operation until the load discharges the output to 101.1% of the set nomi - nal output voltage. most of the internal blocks are turned off in hibernate operation to save quiescent current. after the output falls below 101.1% of the set nominal output voltage, the device comes out of hibernate operation, turns on all internal blocks, and again commences the process of delivering pulses of energy to the output until it reaches 102.3% of the set nominal output voltage. the advantage of the pfm mode is higher efficiency at light loads because of lower quiescent current drawn from supply. the disadvantage is that the output-voltage ripple is higher compared to pwm or dcm modes of operation and switching frequency is not constant at light loads. dcm mode operation dcm mode of operation features constant frequency operation down to lighter loads than pfm mode, not by skipping pulses, but by disabling negative inductor current at light loads. dcm operation offers efficiency performance that lies between pwm and pfm modes. the output-voltage ripple in dcm mode is comparable to pwm mode and relatively lower compared to pfm mode. maxim integrated 17 www.maximintegrated.com max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter
linear regulator (v cc and extvcc) the max17632 has an internal low dropout (ldo) regula - tor that powers v cc from v in . this ldo is enabled during power-up or when en/uvlo is recycled. when v cc is above its uvlo, if extvcc is greater than 4.7v (typ), internal v cc is powered by extvcc and ldo is dis - abled from v in . powering v cc from extvcc increases efficiency at higher input voltages. the typical v cc output voltage is 5v. bypass v cc to sgnd with a 2.2f low- esr ceramic capacitor. v cc powers the internal blocks and the low-side mosfet driver and recharges the exter - nal bootstrap capacitor. the max17632 employs an undervoltage-lockout circuit that forces the regulator off when v cc falls below v cc_ uvf . the regulator can be immediately enabled again when v cc > v cc_uvr . the 400mv uvlo hysteresis prevents chattering on power-up/power-down. in applications where the buck-converter output is con - nected to the extvcc pin, if the output is shorted to ground, then the transfer from extvcc to internal ldo happens seamlessly without any impact to the normal functionality. connect extvcc pin to sgnd, when not in use. setting the switching frequency (rt) the switching frequency of the device can be pro - grammed from 400khz to 2.2mhz by using a resistor con - nected from the rt pin to sgnd. the switching frequency (f sw ) is related to the resistor connected at the rt pin (r rt ) by the following equation: rt sw 21000 r = -1.7 f where r rt is in k and f sw is in khz. leaving the rt pin open makes the device operate at the default switching frequency of 400khz. see table 1 for rt resistor values for a few common switching frequencies. operating input-voltage range the minimum and maximum operating input voltages for a given output voltage setting should be calculated as follows: ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) out out(max) dcr max ds-onl max in(min) sw(max) off-min(max) ds-onh(max) ds-onl(max) out max v + i r +r v = 1 - f t + i r - r out in(max) sw(max) on-min(max) v v = ft where: v out = steady-state output voltage i out(max) = maximum load current r dcr(max) = worst-case dc resistance of the inductor f sw(max) = maximum switching frequency t off-min(max) = worst-case minimum switch off-time (160ns) t on-min(max) = worst-case minimum switch on-time (80ns) r ds-onl(max) and r ds-onh(max) = worst-case on-time resistances of low-side and high-side internal mosfets, respectively. overcurrent protection (ocp)/hiccup mode the device is provided with a robust overcurrent-protection (ocp) scheme that protects the device under overload and output short-circuit conditions. a cycle-by-cycle peak current limit turns off the high-side mosfet whenever the high-side switch current exceeds an internal limit of i peak- limit (3.15a (typ)). a runaway peak current limit on the high-side switch current at i runaway-limit (3.6a (typ)) protects the device under high input voltage, short-circuit conditions when there is insufficient output voltage avail - able to restore the inductor current that built up during the on period of the step-down converter. one occurrence of the runaway current limit triggers a hiccup mode. in addi - tion, if, due to a fault condition, feedback voltage drops to v fb-hicf any time after soft-start is complete and hiccup mode is triggered. in hiccup mode, the converter is pro - tected by suspending switching for a hiccup timeout period of 32,768 clock cycles of half the programmed switch - ing frequency. once the hiccup timeout period expires, soft-start is attempted again. note that when soft-start is attempted under overload condition, if feedback voltage switching frequency (khz) rt resistor (k) 400 open 400 50.8 500 40.2 2200 8.06 table 1. switching frequency vs. rt resistor maxim integrated 18 www.maximintegrated.com max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter
does not exceed v fb-hicf , the device continues to switch at half the programmed switching frequency for the time duration of the programmed soft-start time and 1024 clock cycles. hiccup mode of operation ensures low power dis - sipation under output short-circuit conditions. reset output the device includes a reset comparator to monitor the output voltage. the open-drain reset output requires an external pullup resistor. reset goes high (high imped - ance) 1024 switching cycles after the regulator output increases above 95% of the designed nominal regulated voltage. reset goes low when the regulator output volt - age drops to below 92% of the nominal regulated voltage. reset also goes low during thermal shutdown or when the en/uvlo pin goes below v enf . prebiased output when the device starts into a prebiased output, both the high-side and the low-side switches are turned off so that the converter does not sink current from the output. high- side and low-side switches do not start switching until the pwm comparator commands the first pwm pulse, at which point switching commences. the output voltage is then smoothly ramped up to the target value in alignment with the internal reference. thermal-shutdown protection thermal-shutdown protection limits junction temperature of the device. when the junction temperature of the device exceeds +165oc, an on-chip thermal sensor shuts down the device, allowing the device to cool. the thermal sensor turns the device on again after the junction temperature cools by 10oc. soft-start resets during thermal shutdown. carefully evaluate the total power dissipation (see the power dissipation section) to avoid unwanted triggering of the thermal shutdown during normal operation. applications information input capacitor selection the input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuits switching. the input capacitor rms current requirement (i rms ) is defined by the following equation: ( ) ( ) out in out rms out max in v vv i = i - v where, i out(max) is the maximum load current. i rms has a maximum value when the input voltage equals twice the output voltage (v in = 2 x v out ), so out(max) rms(max) i i = 2 choose an input capacitor that exhibits less than +10c temperature rise at the rms input current for optimal long-term reliability. use low-esr ceramic capacitors with high-ripple-current capability at the input. x7r capacitors are recommended in industrial applications for their tem - perature stability. calculate the input capacitance using the following equation: ( ) out max in sw in i d (1- d) c = fv ? ? where: d = v out /v in is the duty ratio of the controller f sw = switching frequency v in = allowable input-voltage ripple = efficiency in applications where the source is located distant from the device input, an appropriate electrolytic capacitor should be added in parallel to the ceramic capacitor to provide necessary damping for potential oscillations caused by the inductance of the longer input power path and input ceramic capacitor. inductor selection three key inductor parameters must be specified for operation with the device: inductance value (l), inductor saturation current (i sat ) and dc resistance (r dcr ). the switching frequency and output voltage determine the inductor value as follows: out sw v for pwm/dcm mode, l = 1.25 f out sw v for pfm mode, l = 0.833 f where v out and f sw are nominal values and f sw is in hz. select an inductor whose value is nearest to the value calculated by the previous formula. select a low-loss inductor closest to the calculated value with acceptable dimensions and having the lowest possible dc resis - tance. the saturation current rating (i sat ) of the inductor must be high enough to ensure that saturation can occur only above the peak current-limit value of i peak-limit . maxim integrated 19 www.maximintegrated.com max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter
output-capacitor selection x7r ceramic output capacitors are preferred due to their stability over temperature in industrial applications. the output capacitors are usually sized to support a step load of 50% of the maximum output current in the application, so the output-voltage deviation is contained to 3% of the output-voltage change. the minimum required output capacitance can be calculated as follows: step response out out it 1 c = 2v ? response c 0.33 t f ? where: i step = load current step t response = response time of the controller v out = allowable output-voltage deviation f c = target closed-loop crossover frequency f sw = switching frequency. select f c to be 1/10th of f sw if the switching frequency is less than or equal to 800khz. if the switching frequency is more than 800khz, select f c to be 80khz. actual derating of ceramic capacitors with dc-voltage must be consid - ered while selecting the output capacitor. derating curves are available from all major ceramic capacitor vendors. soft-start capacitor selection the device implements adjustable soft-start operation to reduce inrush current. a capacitor connected from the ss pin to sgnd programs the soft-start time. the selected output capacitance (c sel ) and the output voltage (v out ) determine the minimum required soft-start capacitor as follows: -6 ss sel out c 28 10 c v ? the soft-start time (t ss ) is related to the capacitor con - nected at ss (c ss ) by the following equation: ss ss -6 c t = 5.55 10 for example, to program a 1ms soft-start time, a 5.6nf capacitor should be connected from the ss pin to sgnd. note that during start-up, the device operates at half the programmed switching frequency until the output voltage reaches 64.4% of set output nominal voltage. setting the input undervoltage-lockout level the device offers an adjustable input undervoltage-lock - out level. set the voltage at which the device turns on with a resistive voltage-divider connected from v in to sgnd. connect the center node of the divider to en/uvlo. choose r1 to be 3.3m? and then calculate r2 as follows: ( ) inu r1 1.215 r2 = v - 1.215 where v inu is the input-voltage level at which the device is required to turn on. ensure that v inu is higher than 0.8 x v out . if the en/uvlo pin is driven from an external signal source, a series resistance of minimum 1k is rec - ommended to be placed between the output pin of signal source and the en/uvlo pin, to reduce voltage ringing on the line. adjusting output voltage set the output voltage with a resistive voltage-divider connected from the output-voltage node (v out ) to sgnd (see figure 2 ). connect the center node of the divider to the fb pin for max17632c. connect output voltage node (v out ) to fb pin for max17632a and max17632b. use the following procedure to choose the resistive voltage- divider values: calculate resistor r6 from the output to the fb pin as follows: ( ) c out 216 r6 = f c where: r6 is in k f c = crossover frequency is in hz c out = actual capacitance of output capacitor in f. figure 1. setting the input undervoltage lockout v in r1 r2 en/uvlo sgnd maxim integrated 20 www.maximintegrated.com max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter
calculate resistor r7 from the fb pin to sgnd as follows: ( ) out r6 0.9 r7 = v - 0.9 r7 is in k?. power dissipation at a particular operating condition, the power losses that lead to temperature rise of the part are estimated as follows: ( ) ?? ?? ?? ?? ?? ?? out out out p = v x i where: p out = output power = efficiency of the converter r dcr = dc resistance of the inductor (see the typical operating characteristics for more information on effi - ciency at typical operating conditions). for a typical multilayer board, the thermal performance metrics for the package are given below: ja = 38 c/w jc = 10 c/w the junction temperature of the device can be estimated at any given maximum ambient temperature (t a(max) ) from the following equation: ( ) ? ( ) ? note: junction temperatures greater than +125c degrades operating lifetimes. pcb layout guidelines all connections carrying pulsed currents must be very short and as wide as possible. the inductance of these connections must be kept to an absolute minimum due to the high di/dt of the currents. since inductance of a cur - rent-carrying loop is proportional to the area enclosed by the loop, if the loop area is made very small, inductance is reduced. additionally, small-current loop areas reduce radiated emi. a ceramic input filter capacitor should be placed close to the v in pins of the ic. this eliminates as much trace inductance effects as possible and gives the ic a cleaner voltage supply. a bypass capacitor for the v cc pin also should be placed close to the pin to reduce effects of trace impedance. when routing the circuitry around the ic, the analog small signal ground and the power ground for switching cur - rents must be kept separate. they should be connected together at a point where switching activity is minimum. this helps keep the analog ground quiet. the ground plane should be kept continuous (unbroken) as far as possible. no trace carrying high switching current should be placed directly over any ground plane discontinuity. pcb layout also affects the thermal performance of the design. a number of thermal throughputs that connect to a large ground plane should be provided under the exposed pad of the part, for efficient heat dissipation. for a sample layout that ensures first pass success, refer to the max17632 evaluation kit layout available at www. maximintegrated.com. figure 2. setting the output voltage v out r6 r7 fb sgnd maxim integrated 21 www.maximintegrated.com max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter
figure 3. fixed 3.3v output with 400khz switching frequency figure 4. fixed 5v output with 400khz switching frequency typical application circuit fixed 5v output typical application circuit fixed 3.3v output reset en/uvlo v in bst rt mode/sync v cc sgnd ss fb pgnd lx lx v in c5 5600pf extvcc 0.1f 6.8h 22f v out 3.3v, 2a max17632a c2 c4 l1 pgnd 2.2f c3 c1: grm31cr71h225ka88 l1: xal5050-682me for pwm/dcm mode, xal5050-103me for pfm mode c4,c5: grm32er71a226k f sw : 400khz pwm mode: connect mode/sync with sgnd dcm mode: connect mode/sync with v cc pfm mode: leave mode/sync floating ep 22f c5 v in c1 4.5v - 36v 2.2f reset en/uvlo v in bst rt mode/sync v cc sgnd ss fb pgnd lx lx v in c5 5600pf extvcc 0.1f 10h 22f v out 5v, 2a max17632b c2 c4 l1 pgnd 2.2f c3 c1: grm31cr71h225ka88 l1: xal5050-103me for pwm/dcm mode, xal6060-153me for pfm mode c4: grm32er71a226k f sw : 400khz pwm mode: connect mode/sync with sgnd dcm mode: connect mode/sync with v cc pfm mode: leave mode/sync floating ep 2.2f v in c1 6.5v - 36v typical application circuits www.maximintegrated.com max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter
figure 5. adjustable 3.3v output with 400khz switching frequency figure 6. adjustable 5v output with 400khz switching frequency typical application circuit adjustable 3.3v output typical application circuit adjustable 5v output typical application circuits (continued) reset en/uvlo v in bst rt mode/sync v cc sgnd ss fb pgnd lx lx v in c5 5600pf extvcc 0.1f 6.8h 22f v out 3.3v, 2a max17632c v in c2 c4 l1 pgnd 2.2f c3 c1: grm31cr71h225ka88 l1: xal5050-682me for pwm/dcm mode, xal5050-103me for pfm mode c4,c5: grm32er71a226k f sw : 400khz pwm mode: connect mode/sync with sgnd dcm mode: connect mode/sync with v cc pfm mode: leave mode/sync floating 121k? r1 44.2k? r2 ep 22f c5 2.2f c1 4.5v - 36v reset en/uvlo v in bst rt mode/sync v cc sgnd ss fb pgnd lx lx v in c5 5600pf extvcc 0.1f 10h 22f v out 5v, 2a max17632c c2 c4 l1 pgnd 2.2f c3 c1: grm31cr71h225ka88 l1: xal5050-103me for pwm/dcm mode, xal6060-153me for pfm mode c4: grm32er71a226k f sw : 400khz pwm mode: connect mode/sync with sgnd dcm mode: connect mode/sync with v cc pfm mode: leave mode/sync floating 243k? r1 52.3k? r2 ep 2.2f v in c1 6.5v - 36v mm ittd www.maximintegrated.com max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter
part number output voltage (v) pin-package max17632aate+ 3.3 16 tqfn 3mm x 3mm max17632bate+ 5 16 tqfn 3mm x 3mm MAX17632CATE+ adjustable 16 tqfn 3mm x 3mm +denotes a lead(pb)-free/rohs compliant package. typical application circuit adjustable 3.3v output with high frequency (1mhz) design figure 7. adjustable 3.3v output with 1mhz switching frequency ordering information reset en / uvlo v in bst rt mode / sync v cc sgnd ss fb pgnd lx lx v in c 5 5600pf extvcc 0 . 1 f 3 . 3 h 22 f v out 3 . 3 v , 2 a max 17632c c 2 c 4 l 1 pgnd 2 . 2 f c 3 c 1 : grm 21br 71h 105ka12 l 1 : xal 4030- 332 me for pwm / dcm mode , xal 4030- 472 me for pfm mode c 4 : grm 32er 71a 226k f sw : 1 mhz pwm mode : connect mode / sync with sgnd dcm mode : connect mode / sync with v cc pfm mode : leave mode / sync unconnected 121k? r 2 45. 3 k? r 3 ep 19. 1 k? r 1 1 f v in c 1 5 . 5 v - 28v maxim integrated 24 www.maximintegrated.com max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter
revision number revision date description pages changed 0 9/17 initial release revision history ? 2017 maxim integrated products, inc. 25 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifcations without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max17632 4.5v to 36v, 2a, high-effciency, synchronous step-down dc-dc converter for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.

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